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Rev 1; 3/08
I2C, 8-Channel Gamma Buffer with EEPROM
General Description
The DS3508 is a programmable 8-channel gamma voltage generator with one byte of on-chip EEPROM and one byte of SRAM memory per channel. Each channel is composed of an independent 8-bit DAC with an associated EEPROM/SRAM pair. At power-up, nonvolatile (NV) EEPROM gamma data is loaded into its corresponding SRAM register that drives the associated 8-bit DAC. An on-chip control register allows selectable control of writing to SRAM/EEPROM or SRAM only. The DS3508 is designed for low-power operation and draws less than 2mA (typ) from the V DD supply. Programming occurs through an I2C-compatible serial interface with support for speeds up to 400kHz. o 8-Bit Gamma DACs, 8 Channels o 1 Byte EEPROM and 1 Byte SRAM per Channel o Ultra-Low Power (2mA IDD, typ) o 400kbps I2C Interface o 9.0V to 15.5V Analog Supply o 2.7V to 5.5V Digital Supply o 20-Pin TSSOP Package o Address Pin Allows Two DS3508s to Reside on the Same I2C Bus
Features
DS3508
Applications
TFT-LCD Gamma Buffer Industrial Controls
PART DS3508E+
Ordering Information
TEMP RANGE -45C to +95C PIN-PACKAGE 20 TSSOP 20 TSSOP
DS3508E+T&R -45C to +95C +Denotes a lead-free package. T&R = Tape and reel.
Typical Operating Circuit
TOP VIEW
SCL
15.0V 5.0V VCC VDD VHH VHM GM1 GM2 GM3 GM4 LIQUID-CRYSTAL DISPLAY 14.8V 8.0V 8 SOURCE DRIVER
Pin Configuration
1 2 3 4
20 19 18 17
VCC GM1 GM2 GM3 GM4 GM5 GM6 GM7 GM8 N.C.
SDA GND A0 VHH VHM VLM VLL VDD N.C.
DS3508
5 6 7 8 9 10 16 15 14 13 12 11
I2C MASTER
SDA SCL A0 GND
DS3508
GM5 GM6 GM7 GM8 VLL 0.2V VLM 7.0V
TSSOP
________________________________________________________________ Maxim Integrated Products
1
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I2C, 8-Channel Gamma Buffer with EEPROM DS3508
ABSOLUTE MAXIMUM RATINGS
Voltage Range on VDD and VHH Relative to GND ..........................................-0.5V to +16V Voltage Range on VHM, VLM, and VLL Relative to GND............................................-0.5V to +12V Voltage Range on VCC, SDA, SCL, and A0 Relative to GND ............................................-0.5V to +6.0V Junction Temperature ......................................................+125C Operating Temperature Range ...........................-45C to +95C Programming Temperature Range .........................0C to +70C Storage Temperature ..........................................55C to +125C Soldering Temperature ..............................................Refer to the IPC/JEDEC J-STD-020 Specification.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -45C to +95C)
PARAMETER Analog Supply Voltage VHH, VHM VLM, VLL VHH-VHM and VLM-VLL Digital Voltage Supply Input Logic 0 (A0, SDA, SCL) Input Logic 1 (A0, SDA, SCL) VREF VCC VIL VIH 0.7 x VCC (Note 1) SYMBOL VDD (Note 1) Applies to GM1-GM4 Applies to GM5-GM8 CONDITIONS MIN +9.0 VDD/2 - 1 0.2 3.0 2.7 5.5 0.3 x VCC TYP MAX +15.5 VDD - 0.2 VDD/2 + 1 UNITS V V V V V V V
INPUT ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -45C to +95C.)
PARAMETER Analog Supply Current Digital Supply Current, NV Read or Write Digital Supply Standby Current Input Leakage (SDA, SCL, A0) Input Resistance at VHH, VHM, VLM, VLL SYMBOL IDD ICC I STBY I IL RIN CONDITIONS VDD = 15.5V (Note 2) f SCL = 400kHz VCC = 5.5V (Note 3) VCC = 5.5V -1 1 MIN TYP 2 0.2 2 MAX 4 1.0 10 +1 UNITS mA mA A A M
2
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I2C, 8-Channel Gamma Buffer with EEPROM
OUTPUT ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V; VDD = 15.5V, TA = -45C to +95C, unless otherwise noted.)
PARAMETER Gamma DAC Resolution Integral Nonlinearity Error Differential Nonlinearity Error Output Voltage Range: GM1-GM4 Output Voltage Range: GM5-GM8 ROUT (GM1-GM8) Amplifier Offset ROUT (Notes 6, 7) TA = +25C (Note 8) -35 TA = +25C (Note 4) TA = +25C (Note 5) SYMBOL CONDITIONS MIN 8 -1.25 -0.5 VHM VLL 20 +35 +1.25 +0.5 VHH VLM TYP MAX UNITS Bits LSB LSB V V k mV
DS3508
I2C ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -45C to +95C, timing referenced to VIL(MAX) and VIH(MIN).) (Figure 4)
PARAMETER SCL Clock Frequency Low Period of SCL High Period of SCL Bus Free Time Between STOP and START Conditions START Setup Time Hold Time (Repeated) START Condition Data Hold Time Data Setup Time A0 Setup Time A0 Hold Time SDA and SCL Rise Time SDA and SCL Fall Time STOP Setup Time SDA and SCL Capacitive Loading EEPROM Write Time SCL Falling Edge to SDA Output Data Valid Output Data Hold SYMBOL f SCL tLOW tHIGH tBUF t SU:STA tHD:STA tHD:DAT t SU:DAT t SU:A tHD:A tR tF t SU:STO CB tW tAA tDH (Note 10) (Note 11) SCL falling through VIL to SDA exit 0.3-0.7 x VCC window SCL falling through VIL until SDA in 0.3-0.7 x VCC window 0 Before START After STOP (Note 10) (Note 10) SCL rising through VIH to SDA falling through VIH SDA falling through VIL to SCL falling through VIH (Note 9) Measured at VIL Measured at VIH CONDITIONS MIN 0 1.3 0.6 1.3 0.6 0.6 0 100 0.6 0.6 20 + (0.1 x CB) 20 + (0.1 x CB) 0.6 400 20 900 300 300 0.9 TYP MAX 400 UNITS kHz s s s s s s ns s s ns ns s pF ms ns ns
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I2C, 8-Channel Gamma Buffer with EEPROM DS3508
I2C ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.7V to +5.5V, TA = -45C to +95C, timing referenced to VIL(MAX) and VIH(MIN).) (Figure 4)
PARAMETER SDA Output Low Voltage Input Capacitance on A0, SDA, or SCL SYMBOL VOL CI CONDITIONS 4mA sink current 6mA sink current 5 MIN TYP MAX 0.4 V 0.6 10 pF UNITS
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = +2.7V to +5.5V)
PARAMETER EEPROM Write Cycles SYMBOL TA = +70C CONDITIONS MIN 50,000 TYP MAX UNITS Writes
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Note 9: Note 10: Note 11:
All voltages referenced to ground. Analog supply current specified with no load on GMx outputs. ISTBY specified for the inactive state measured with SDA = SCL = VCC. INL = [V(GMx)i - (V(GMx)0]/LSB(ideal) - i, for i = 0 to 254. DNL = [V(GMx)i+1 - (V(GMx)i]/LSB(ideal) - 1, for i = 0 to 255. DAC code = 80h. Outputs unloaded. VHH = 12.0V, VHM = 8.75V, VLM = 6.75V, VLL = 0.5V. Timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard mode. CB--Total capacitance of one bus line in picofarads. EEPROM write begins after a STOP condition occurs.
Typical Operating Characteristics
(VDD = 15.0V, VCC = 5.0V, TA = +25C, unless otherwise noted.)
DIGITAL SUPPLY STANDBY CURRENT vs. DIGITAL SUPPLY VOLTAGE
DS3508 toc01
DIGITAL SUPPLY STANDBY CURRENT vs. TEMPERATURE
9 8
ICC STBY CURRENT (A)
ANALOG SUPPLY CURRENT vs. ANALOG SUPPLY VOLTAGE
DS3508 toc02
9 8
ICC STBY CURRENT (A)
SDA = SCL = VCC
VCC = 5.5V SDA = SCL = VCC
3.5 3.0
IDD CURRENT (mA)
7 6 5 4 3 2 1 0 2.0 2.5 3.0 3.5 4.0 VCC (V) 4.5 5.0 5.5 6.0
7 6 5 4 3
2.5 2.0 1.5 1.0
2 1 0 -45 -25 -5 15 35 55 75 95 TEMPERATURE (C) 0.5 0 8 10 12 VDD (V) 14 16
4
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DS3508 toc03
10
10
4.0
I2C, 8-Channel Gamma Buffer with EEPROM
Typical Operating Characteristics (continued)
(VDD = 15.0V, VCC = 5.0V, TA = +25C, unless otherwise noted.)
ANALOG SUPPLY CURRENT vs. TEMPERATURE
DS3508 toc04
DS3508
GAMMA OUTPUT vs. SETTING
DS3508 toc05
GAMMA OFFSET vs. TEMPERATURE
8 6
GM OFFSET (mV)
DS3508 toc06
4.0 3.5 3.0
IDD CURRENT (mA)
15
10 GM1 = VHH = 14.5V GM1 = VHH = 12.0V
12 2.5 2.0 1.5 1.0 3 0.5 0 -45 -25 -5 15 35 55 75 95 TEMPERATURE (C) 0 0 32 64 96
GM OUTPUT (V)
GM1-GM4 VDD = 15.0V VHH = 14.8V VHM = 8.0V VLM = 7.0V VLL = 0.2V
4 2 0 -2 -4 GM8 = VLM = 8.5V GM8 = VLL = 0.5V GM1 = VHM = 6.5V -8 -10
9
6
GM5-GM8
-6
128 160 192 224 256
-45
-25
-5
15
35
55
75
95
GAMMA SETTING (DEC)
TEMPERATURE (C)
GM1 DNL
DS3508 toc07
GM1 INL
DS3508 toc08
GM8 DNL
VDD = 15.0V VLM = 7.0V VLL = 0.2V
DS3508 toc09
1.00 0.75 0.50
GM1 DNL (LSB)
1.00 0.75 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 VDD = 15.0V VHH = 14.8V VHM = 8.0V
1.00 0.75 0.50
GM8 DNL (LSB)
VDD = 15.0V VHH = 14.8V VHM = 8.0V
0.25 0 -0.25 -0.50 -0.75 -1.00 0 32 64 96 128 160 192 224 256 GAMMA SETTING (DEC)
GM1 INL (LSB)
0.25 0 -0.25 -0.50 -0.75 -1.00
0
32
64
96
128 160 192 224 256
0
32
64
96
128 160 192 224 256
GAMMA SETTING (DEC)
GAMMA SETTING (DEC)
GM8 INL
VDD = 15.0V VLM = 7.0V VHM = 0.2V
DS3508 toc10
1.00 0.75 0.50
GM8 INL (LSB)
0.25 0 -0.25 -0.50 -0.75 -1.00 0 32 64 96 128 160 192 224 256 GAMMA SETTING (DEC)
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I2C, 8-Channel Gamma Buffer with EEPROM DS3508
Functional Diagram
VDD VDD VHH
SRAM 1 VCC VCC SDA SCL A0 I2C INTERFACE EEPROM 2 SRAM 3 CONTROL LOGIC CONTROL REGISTERS VHM EEPROM 1 SRAM 2
8-BIT DAC
GM1
8-BIT DAC
GM2
8-BIT DAC
GM3
EEPROM 3 SRAM 4 8-BIT DAC GM4
EEPROM 4
VLM
SRAM 5
8-BIT DAC
GM5
EEPROM 5 SRAM 6 8-BIT DAC GM6
EEPROM 6 SRAM 7 8-BIT DAC GM7
EEPROM 7 SRAM 8 8-BIT DAC GM8
VLL
EEPROM 8
GND
DS3508
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I2C, 8-Channel Gamma Buffer with EEPROM
Pin Description
PIN 1 2 3 4 5 6 7 8 9 10, 11 12 13 14 15 16 17 18 19 20 NAME SCL SDA GND A0 VHH VHM VLM VLL VDD N.C. GM8 GM7 Output GM6 GM5 GM4 GM3 Output GM2 GM1 VCC Power Digital Supply Gamma Analog Outputs 1-4. These pins are the high-voltage gamma outputs referenced to VHH and VHM. Gamma Analog Outputs 5-8. These pins are the low-voltage gamma outputs referenced to VLL and VLM. TYPE Input Input/ Output Ground Input Reference Input Reference Input Reference Input Reference Input Power -- Serial Clock Input. I2C clock input. Serial Data Input/Output (Open Drain). I2C bidirectional data pin that requires a pullup resistor to realize high logic levels. Ground Address Input. Determines I2C slave address. High-Voltage DAC, Upper Reference High-Voltage DAC, Lower Reference Low-Voltage DAC, Upper Reference Low-Voltage DAC, Lower Reference Analog Supply No Connection FUNCTION
DS3508
Detailed Description
The DS3508 provides eight independent DACs that allow precise and repeatable setting of gamma curves. The DS3508 provides four high-voltage DACs (GM1-GM4) that operate between VHH and VHM and four low-voltage DACs (GM5-GM8) that operate between VLM and VLL. Each of the DACs provides 8 bits of resolution. The DS3508 DAC output voltages are independently controlled by the data stored in that channel's SRAM register. The MODE bit in the volatile control register (CR bit 7) determines how I 2C data is written to the SRAM and EEPROM gamma data registers. Reading and writing to the SRAM/EEPROM gamma data registers is based on the state of the MODE bit as follows:
I 2 C writes to memory addresses 00h-07h write to both SRAM 1-8 and EEPROM 1-8. I 2 C reads from addresses 00h-07h read from SRAM 1-8. MODE = 1: I2C writes to addresses 00h-07h write to SRAM 1-8. I 2 C reads from addresses 00h-07h read from SRAM 1-8. Regardless of the MODE bit setting, all I2C reads of address 00-07h return the contents of the SRAM registers. Setting MODE = 1 allows for quick writing of SRAM without the added delay of writing to the associated EEPROM register. The data that is stored in EEPROM and SRAM remains unchanged if the MODE bit is toggled. MODE = 0:
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I2C, 8-Channel Gamma Buffer with EEPROM DS3508
On power-up, the gamma data that is stored in each channel's EEPROM register is loaded into the corresponding SRAM registers. The volatile CR register powers up as 00h, setting the device into mode 0. with end points VHH and VHM controls outputs GM1-GM4, and a low-voltage array with end points VLM and VLL controls outputs GM5-GM8. The resistor string arrays are composed of 255 identical resistors. The switching networks can select any tap point between adjacent resistors as well as either end point (VHH/VHM or VLM/VLL pins). Table 1 shows the relationship between the 8-bit data and the DAC voltage.
DAC Description
The DACs are composed of a resistor string array and a switching network per channel. A high-voltage array
SDA SCL A0
I2C INTERFACE
SRAM
8-BIT DAC
GMx
EEPROM
Figure 1. Single-Channel Block Diagram
VHH CODE 0 RH1 CODE 1 RH2 CODE 2 RH3
VLL CODE 0 RL1 CODE 1 RL2 CODE 2 RL3
RH253 CODE 253 RH254 CODE 254 RH255 VHM CODE 255 VLM
RL253 CODE 253 RL254 CODE 254 RL255 CODE 255
Figure 2. DAC Block Diagram
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I2C, 8-Channel Gamma Buffer with EEPROM
Table 1. DAC Voltage/Data Relationship for Selected Codes
DATA (BINARY) 0000 0000 0000 0001 0000 0010 0000 0011 0000 1111 0011 1111 0111 1111 1111 1101 1111 1110 1111 1111 OUTPUT VOLTAGE GM1-GM4 VHH VHH + 1 x (VHM - VHH)/255 VHH + 2 x (VHM - VHH)/255 VHH + 3 x (VHM - VHH)/255 VHH + 15 x (VHM - VHH)/255 VHH + 63 x (VHM - VHH)/255 VHH + 127 x (VHM - VHH)/255 VHH + 253 x (VHM - VHH)/255 VHH + 254 x (VHM - VHH)/255 VHM GM5-GM8 VLL VLL+ 1 x (VLM - VLL)/255 VLL + 2 x (VLM - VLL)/255 VLL + 3 x (VLM - VLL)/255 VLL + 15 x (VLM - VLL)/255 VLL + 63 x (VLM - VLL)/255 VLL + 127 x (VLM - VLL)/255 VLL + 253 x (VLM - VLL)/255 VLL + 254 x (VLM - VLL)/255 VLM
DS3508
Slave Address Byte and Address Pin
MSB 1 1 1 0 1 0 A0 LSB R/W
SLAVE ADDRESS*
READ/WRITE BIT
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PIN A0.
Figure 3. DS3508 Slave Address Byte
The slave address byte consists of a 7-bit slave address plus a R/W bit (see Figure 3). The DS3508's slave address is determined by the state of the A0 pin. This pin allows up to two devices to reside on the same I2C bus. Connecting A0 to GND results in a 0 in the corresponding bit position in the slave address. Conversely, connecting A0 to VCC results in a 1 in the corresponding bit position. For example, the DS3508's slave address byte is E8h when A0 is grounded. I2C communication is described in detail in the I2C Serial Interface Description section.
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I2C, 8-Channel Gamma Buffer with EEPROM DS3508
Memory Organization
Memory Description
The list of registers/memory contained in the DS3508 is shown in the memory map (Table 2). Each of the GMx registers also has a corresponding NV EEPROM register. Additional information regarding reading and writing the memory is located in the I2C Serial Interface Description section.
Table 2. Memory Map
NAME GM1 GM2 GM3 GM4 GM5 GM6 GM7 GM8 Control Register Reserved ADDRESS (HEX) 00 01 02 03 04 05 06 07 08 09-FF SRAM SRAM1 (8 bits) SRAM2 (8 bits) SRAM3 (8 bits) SRAM4 (8 bits) SRAM5 (8 bits) SRAM6 (8 bits) SRAM7 (8 bits) SRAM8 (8 bits) Volatile Control Register Reserved EEPROM EEPROM1 (8 bits) EEPROM2 (8 bits) EEPROM3 (8 bits) EEPROM4 (8 bits) EEPROM5 (8 bits) EEPROM6 (8 bits) EEPROM7 (8 bits) EEPROM8 (8 bits) N/A Reserved
*All EEPROM1-8 is factory-programmed to 80h.
Detailed Register Description
Register 08h: Control Register (CR)
POWER-UP DEFAULT MEMORY TYPE 00h Volatile
08h
MODE Bit 7
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved Bit 0
Bit 7 Bits 6 to 0
MODE 0 = (Default) I2C writes to both SRAM and EEPROM. MODE 1 = I2C writes to SRAM only. Reserved.
This bit determines if data is written to EEPROM and SRAM or only SRAM.
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I2C, 8-Channel Gamma Buffer with EEPROM
I2C Serial Interface Description
I2C Definitions
The following terminology is commonly used to describe I2C data transfers. (See Figure 4 and the I2C Electrical Characteristics table for additional information.) Master device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses and START and STOP conditions. Slave devices: Slave devices send and receive data at the master's request. Bus idle or not busy: Time between STOP and START conditions when both SDA and SCL are inactive and in their logic-high states. START condition: A START condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a START condition. STOP condition: A STOP condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a STOP condition. Repeated START condition: The master can use a repeated START condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated STARTS are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated START condition is issued identically to a normal START condition. Bit write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold time requirements. Data is shifted into the device during the rising edge of the SCL. Bit read: At the end of a write operation, the master must release the SDA bus line for the proper amount of setup time before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses, including when it is reading bits from the slave. Acknowledge (ACK and NACK): An Acknowledge (ACK) or Not Acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a 0 during the 9th bit. A device performs a NACK by transmitting a 1 during the 9th bit. Timing for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or indicates that the device is not receiving data. Byte write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgment from the slave to the master. The 8 bits transmitted by the master are done according to the bit write definition and the acknowledgment is read using the bit read definition.
DS3508
SDA
tBUF tLOW tR tF
tHD:STA
tSP
SCL tHD:STA STOP START tHD:DAT tHIGH tSU:DAT REPEATED START tSU:STA tSU:STO
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
Figure 4. I2C Timing Diagram ______________________________________________________________________________________ 11
I2C, 8-Channel Gamma Buffer with EEPROM
Byte read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to terminate communication so the slave returns control of SDA to the master. Slave address byte: Each slave on the I 2 C bus responds to a slave address byte sent immediately following a START condition. The slave address byte contains the slave address in the most significant 7 bits and the R/W bit in the least significant bit. The DS3508's slave address is determined by the state of the A0 address pin as shown in Figure 3. An address pin connected to GND results in a 0 in the corresponding bit position in the slave address. Conversely, an address pin connected to VCC results in a 1 in the corresponding bit positions. When the R/W bit is 0 (such as in E8h), the master is indicating that it will write data to the slave. If R/W = 1 (E9h in this case), the master is indicating that it wants to read from the slave. If an incorrect slave address is written, the DS3508 assumes the master is communicating with another I2C device and ignores the communication until the next START condition is sent. Memory address: During an I2C write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte. Writing multiple bytes to a slave: To write multiple bytes to a slave in one transaction, the master generates a START condition, writes the slave address byte (R/W = 0), writes the starting memory address, writes up to 4 data bytes, and generates a STOP condition. The DS3508 can write 1 to 4 bytes (1 page or row) in a single write transaction. This is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. The address counter limits the write to one 4-byte page. The first page begins at address 00h and the second page begins at 04h. Attempts to write to additional pages of memory without sending a STOP condition between pages results in the address counter wrapping around to the beginning of the present row. To prevent address wrapping from occurring, the master must send a STOP condition at the end of the page, then wait for the bus-free or EEPROM-write time to elapse. Then the master can generate a new START condition, and write the slave address byte (R/W = 0) and the first memory address of the next memory row before continuing to write data. Acknowledge polling: Any time a EEPROM byte is written, the DS3508 requires the EEPROM write time (tW) after the STOP condition to write the contents of the byte to EEPROM. During the EEPROM write time, the device does not acknowledge its slave address because it is busy. It is possible to take advantage of this phenomenon by repeatedly addressing the DS3508, which allows communication to continue as soon as the DS3508 is ready. The alternative to acknowledge polling is to wait for a maximum period of tW to elapse before attempting to access the device. Reading a single byte from a slave: Unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. To read a single byte from the slave, the master generates a START condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a STOP condition. However, since requiring the master to keep track of the memory address counter is impractical, the following method should be used to perform reads from a specified memory location. Reading multiple bytes from a slave: The read operation can be used to read multiple bytes with a single transfer. When reading bytes from the slave, the master simply ACKs the data byte if it desires to read another
DS3508
I2C Communication
See Figure 5 for I2C communication examples. Writing a single byte to a slave: The master must generate a START condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a STOP condition. Remember the master must read the slave's acknowledgment during all byte write operations. When writing to the DS3508, the DAC adjusts to the new setting following a STOP. The EEPROM (used to make the setting NV) is written following the STOP condition at the end of the write command if the MODE bit is set to 0.
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I2C, 8-Channel Gamma Buffer with EEPROM DS3508
TYPICAL I2C WRITE TRANSACTION MSB START 1 1 1 0 1 0 A0 LSB R/W SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK STOP
SLAVE ADDRESS*
READ/ WRITE
REGISTER ADDRESS *THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PIN A0.
DATA
EXAMPLE I2C TRANSACTIONS (WHEN A0 IS CONNECTED TO GND) E8h A) SINGLE-BYTE WRITE -WRITE CR REGISTER TO 80h START 1 1 1 0 1 0 0 0 08h SLAVE 00001000 ACK 02h SLAVE SLAVE 00000010 ACK ACK REPEATED START 80h SLAVE 10000000 ACK SLAVE ACK E9h 11101001 SLAVE ACK STOP
E8h B) SINGLE-BYTE READ -READ GM3 START 1 1 1 0 1 0 0 0
DATA GM3 MASTER NACK STOP
E8h C) TWO-BYTE WRITE - WRITE GM1 AND GM2 TO 80h START 1 1 1 0 1 0 0 0
00h SLAVE SLAVE 00000000 ACK ACK
80h 1000 0 0 0 0 SLAVE ACK
80h 10000000 SLAVE ACK STOP
E8h D) TWO-BYTE READ - READ GM1 AND GM2 START 1 1 1 0 1 0 0 0
00h SLAVE SLAVE 00000000 ACK ACK
E9h REPEATED START 11101001 SLAVE ACK
DATA GM1 MASTER ACK
DATA GM2 MASTER NACK STOP
Figure 5. I2C Communication Examples
byte before terminating the transaction. After the master reads the last byte it must NACK to indicate the end of the transfer and generates a STOP condition. Manipulating the address counter for reads: A dummy write cycle can be used to force the address counter to a particular value. To do this the master generates a START condition, writes the slave address byte (R/W = 0), writes the memory address where it desires to read, generates a repeated START condition, writes the slave address byte (R/W = 1), reads data with ACK or NACK as applicable, and generates a STOP condition. The master must NACK the last byte to inform the slave that no additional bytes are to be read.
components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications.
SDA and SCL Pullup Resistors
SDA is an I/O with an open-collector output that requires a pullup resistor to realize high-logic levels. A master using either an open-collector output with a pullup resistor or a push-pull output driver can be used for SCL. Pullup resistor values should be chosen to ensure that the rise and fall times listed in the electrical characteristics are within specification. A typical value for the pullup resistors is 4.7k.
Applications Information
Power-Supply Decoupling
To achieve the best results when using the DS3508, decouple both power-supply pins (VCC and VDD) with a 0.01F or 0.1F capacitor. Use a high-quality ceramic surface-mount capacitor if possible. Surface-mount
Package Information
(For the latest package outline information, go to www.maxim-ic.com/DallasPackInfo.) PACKAGE TYPE 20 TSSOP PACKAGE CODE -- DOCUMENT NO. 56-G2010-000
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I2C, 8-Channel Gamma Buffer with EEPROM DS3508
Revision History
REVISION NUMBER 0 1 REVISION DATE 1/08 3/08 Initial release. In the Nonvolatile Memory Characteristics table, removed TA = +25C 200,000 write cycle specification for EEPROM write cycles. DESCRIPTION PAGES CHANGED -- 4
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2008 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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